Semiconductor read-only VLSI memory

Details Semiconductor read-only VLSI memory Semiconductor read-only VLSI memory

1995-05-05

1996-12-03

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By phase

327252, 327530, H03H 1116

Patent

active

055812031

ABSTRACT:
The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by improvements in various circuits and methodologies utilized in the memory. Appropriate bias levels are generated by a bias circuit for use in the output buffer according to whether a process temperature and voltage variations within the memory circuit are such that variation sensitive components will be slowed upon the occurrence of such variations. The bias circuit otherwise generates a bias signal appropriate for fast speed operations within the output buffer circuit when process temperature and voltage variations are such that they do not effect circuit speed of sensitive circuit portions. The back bias generator which operates asynchronously from the memory cycle is improved by disabling the charge pumping action during a memory cycle.

REFERENCES:
patent: 4338569 (1982-07-01), Petrich
patent: 5073886 (1991-12-01), Sasaki et al.
patent: 5295164 (1994-03-01), Yamamura
patent: 5336940 (1994-08-01), Sorrells et al.
patent: 5345119 (1994-09-01), Khoury
patent: 5351000 (1994-08-01), Farwell

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