Store queue for a tightly coupled multiple processor configurati

Details Store queue for a tightly coupled multiple processor configurati Store queue for a tightly coupled multiple processor configurati

1988-02-22

1991-06-11

Shaw, Gareth D.

Boots, shoes, and leggings

3642344, 36424341, 36424345, 3642443, 3642545, 36424344, G06F 1300

Patent

active

050237764

ABSTRACT:
A multiprocessor system includes a system of store queues and write buffers in a hierarchical first level and second level memory system including a first level store queue for storing instructions and/or data from a processor of the multiprocessor system prior to storage in a first level of cache, a second level store queue for storing the instructions and/or data from the first level store queue and a plurality of write buffers for storing the instructions and/or data from the second level store queue prior to storage in a second level of cache. The multiprocessor system includes hierarchical levels of caches, including a first level of cache associated with each processor, a single shared second level of cache shared by all the processors, and a third level of main memory connected to the shared second level cache. A first level store queue, associated with each processor, receives the data and/or instructions from its processor and stores the data and/or instructions in the first level of cache. A second level store queue, associated with each processor, receives the data and/or instructions from its first level store queue and temporarily stores the information therein. For sequential stores, the data and/or instructions are stored in corresponding second level write buffers. For non-sequential stores, the data and/or instructions bypass the corresponding second level write buffers and are stored directly in a final L2 cache write buffer. When stored in the second level writer buffers, access to the shared second level cache is requested.

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