PIN-FET combination with buried p-layer

Details PIN-FET combination with buried p-layer PIN-FET combination with buried p-layer

1990-06-15

1991-06-11

Mintel, William

357 19, 357 16, 357 41, 357 55, 357 47, H01L 2714

Patent

active

050236865

ABSTRACT:
A PIN-FET combination having a basic layer, a first semiconductor layer as an absorption layer or, resepectively, a buffer layer, a second semiconductor layer as a contact layer or, respectively, as a channel layer and a third semiconductor layer as a cover layer grown surface-wide on a substrate. The p.sup.+ -region of the photodiode and, respectively, the gate region of the FET being fashioned therein. The basic layer is undoped or n-doped in the region of the photodiode and is p-doped in the region of the FET and a surface-wide, p-doped layer portion is present in the region of the FET between the channel layer and the substrate.

REFERENCES:
patent: 4821090 (1989-04-01), Yokoyama
Albrecht, "Monolithically Integrated InGaAs/InP:Fe Photodiode-Junction Field Effect Transistor Combination," Siemens Forsch.-M. Entwickl.-Ber., vol. 17, No. 4, (1988), pp. 195-198, Mar. 23.
Miura et al., "A Monolithically Integrated AlGaAs/GaAs P-I-N/FET Photoreceiver by MOCVD," IEEE Electron Device Letters, vol. EDL-4, No. 10, Oct. 1983, pp. 375-376.
Anderson et al., "Planar, Linear GaAs Detector-Amplifier Array with an Insulating AlGaAs Spacing Layer Between the Detector and Transistor Layers", IEEE Electron Device Ltrs., vol. 9, No. 10, Oct. 1988, pp. 550-552.
Chen et al., "A Strip-Geometry InGaAs P/InP Heterojunction Bipolar Transistor Suitable for Optical Integration," IEEE Electronic Device Letters, vol. EDL-8, No. 5, May 1987, pp. 191-193.
Steiner et al., "Influence of P-INP Buffer Layers on Submicron in GaAs/INP Junction Field-Effect Transistors", Am. Inst. of Physics, Dec. 19, 1988, pp. 2513-2515.

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