Patent
1989-09-08
1991-06-11
Mintel, William
357 55, 357 56, 357 41, H01L 2968, H01L 2906, H01L 2702
Patent
active
050236830
ABSTRACT:
A semiconductor memory device having an improved capacitor configuration is provided in which storage node electrodes are formed projecting perpendicularly with respect to a substrate. Thus, the surface areas of the storage node electrodes are enlarged. As a result, memory cell chip areas can be minimized while maintaining the prescribed capacitance of storage capacitors. Further, a method of manufacturing the device is also provided.
REFERENCES:
patent: 4785337 (1989-11-01), Kenney
patent: 4855801 (1989-08-01), Kuesters
Technical Digest of Conference on Solid State Devices and Materials, pp. 581-584, "A Novel Storage Capacitance Enlargement Structure Using a Double-Stacked Storage Node in STC DRAM Cell", T. Kisu et al, 1988.
Kabushiki Kaisha Toshiba
Mintel William
Potter R.
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