Method of making EEPROM devices with smaller cell size

Details Method of making EEPROM devices with smaller cell size Method of making EEPROM devices with smaller cell size

1995-09-08

1996-05-28

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 49, 437 70, 437984, H01L 218247

Patent

active

055211100

ABSTRACT:
An EEPROM and method for making the same, having precisely shaped field oxide regions and memory cells, to provide improved electrical operating characteristics and increased memory density. A layer of field oxide is grown over an n-type substrate having a p-well and the layer of field oxide is selectively etched to form rows of field oxide. Rows of tunnel oxide are formed between the rows of field oxide. A first layer of polysilicon, or poly-1, is formed over the wafer and a layer of ONO is formed over the poly-1. Using the same mask, the ONO, poly-1, field oxide, and tunnel oxide are stack etched. Bit lines are formed, followed by oxide spacers. A second layer of polysilicon,or poly-2 is formed and selectively etched to form word lines. The exposed ONO and poly-1 are etched using the same mask to form floating gate regions. Subsequent process steps provide word lines to metal dielectric, contacts, metal and passivation.

REFERENCES:
patent: 5091326 (1992-02-01), Haskell
patent: 5151375 (1992-09-01), Kazerounion et al.
patent: 5371031 (1994-12-01), Gill et al.

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