Processing unit containing DMA controller having concurrent oper

Details Processing unit containing DMA controller having concurrent oper Processing unit containing DMA controller having concurrent oper

1991-07-03

1992-08-04

Anderson, Lawrence E.

Boots, shoes, and leggings

3642329, 3642424, G06F 1314

Patent

active

051367017

ABSTRACT:
A processing unit containing a DMA controller comprises a 2nb (n.gtoreq.1) processor data bus (6), a 2nb DMA data bus (7), a 2nb (m.gtoreq.1) processor address bus (8), and a 2nb DMA address bus (9). These buses have a plurality of latch circuits (51-54) respectively connected thereto. One of the processor and DMA data latched in each latch circuit, and one of the processor and DMA addresses are selected by a first multiplexer (55, 56). The 2nb data and 2mb data from the output of the first multiplexer and the outputs of the latch circuits are divided into sets of nb and mb, respectively; thus they are given in the form of 3 inputs to a second multiplixer (57-60). When the processor and the DMA controller concurrently operate, data and address are transferred without keeping one of them waiting.

REFERENCES:
patent: 4920480 (1990-04-01), Murakami et al.
patent: 5045993 (1991-09-01), Murakami et al.

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