Methods and apparatus for caching interlock variables in an inte

Details Methods and apparatus for caching interlock variables in an inte Methods and apparatus for caching interlock variables in an inte

1988-01-20

1992-08-04

Kriess, Kevin A.

Boots, shoes, and leggings

364DIG1, 3642283, 3642434, 3642815, G06F 1516, G06F 1300

Patent

active

051366916

ABSTRACT:
Methods and apparatus are disclosed for supporting the caching of interlock variables in cache memory units employed in multiprocessor and/or multitasking environments. The preferred embodiment of the invention includes methods and apparatus for selectively treating interlock variables as cachable or non-cachable. The disclosed methods and apparatus are suitable for supporting high speed data and instruction processing applications in both RISC and non-RISC architecture environments, can be integrated on a single chip and allows for better performance and utilization of the computer system bus structure since most of the interlock variable accesses are faster and do not appear on the memory bus (only in the cache).

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IBM Technical Disclosure Bulletin, vol. 28, No. 3, Aug. 1985, pp. 1169-1174.

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