Memory with isolated digit lines

Details Memory with isolated digit lines Memory with isolated digit lines

1993-04-20

1994-11-29

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sync/clocking

365190, 365194, 365207, G11C 700

Patent

active

053696220

ABSTRACT:
A memory in which a portion of a digit line is isolated from the remainder of the digit line during a write cycle has improved performance. In the conventional architecture of a memory device, cells are arranged in rows and columns and a sense amplifier is employed for a pair of columns, located between a pair of complementary digit lines. An embodiment of the present invention in this architecture provides improved means for isolating the sense amplifier during a write cycle.

REFERENCES:
patent: 4636987 (1987-01-01), Norwood et al.
patent: 4748349 (1988-05-01), McAlexander, III et al.
patent: 5014245 (1991-05-01), Muroka et al.
patent: 5029137 (1991-07-01), Hoshi
patent: 5193075 (1993-03-01), Hatano et al.
patent: 5235547 (1993-08-01), Kobayashi

Affiliated with

Also associated with

Rating

Memory with isolated digit lines does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory with isolated digit lines, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory with isolated digit lines will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-78584