Static information storage and retrieval – Addressing
Patent
1993-02-02
1994-11-29
Fears, Terrell W.
Static information storage and retrieval
Addressing
36523003, 36523008, G11C 1300
Patent
active
053696182
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates to a serial I/O serial access memory useful in a speech processing unit, an image processing unit, a computer system or the like.
BACKGROUND ART
Speech processing units, image processing units, computer systems equipped with a central processing unit (CPU), and the like require a large-capacity memory for the storage of data. This memory is desired to permit high-speed writing and reading and also to have a low production cost. As memories capable of satisfying these requirements, serial access memories are now receiving attention. They are introduced in "Variety of Field-Memory-Dedicated 1M Chips Now Available for VTRs and TVs" Nikkei Electronics, 421, 147-162, NIKKEI McGRAW-HILL, INC., May 18, 1987. To facilitate the understanding of the present invention, the construction and operation of a popular serial memory will hereinafter be described with reference to FIG. 1 through FIG. 4.
FIG. 1 is a simplified block diagram of the popular serial access memory. Different from general DRAMs, a serial access memory permits high-speed serial input and serial output without sequential input of Y addresses (column addresses). To continuously perform a serial output or serial input, the serial access memory has two memory banks A1,A2 of the same construction.
The memory banks A1,A2 are provided with (m,n) memory matrices 10-1,10-2, X addressing means 11-1,11-2 and serial access means 20-1,20-2, respectively. The memory matrices 10-1,10-2 have m word lines WL1-1 to WL1-m,WL2-1 to WL2-m and n bit lines BL1-1 to BL1-n, BL2-1 to BL2-n, respectively. Although not illustrated, there are memory cells disposed in the vicinity of intersections of the word lines and the bit lines and connected to the adjacent word lines and bit lines, respectively. These plural word lines WL1-1 to WL1-m,WL2-1 to WL2-m are selected by the X addressing means 11-1,11-2 which decode X addresses (row addresses). By this word line selection, unillustrated plural memory cells connected, for example, to the word lines WL1-j,WL2-j (j=natural number of 1-m) are electrically connected with adjacent bit lines BL1-1 to BL1-n, BL2-1 to BL2-n so that the plural memory cells are accessed by the serial access means 20-1,20-2 of n.times.1 bits which automatically generate serial addresses on the basis of a serial clock signal CLK. Incidentally, the respective bit lines BL1-1 to BL2-n are illustrated as single lines in FIG. 1 with a view toward simplifying their description. In truth, however, each bit line is formed of a pair of bit lines BL,BL which develop a potential in a complementary relation in an active state as illustrated in FIG. 2. The memory matrices 10-1,10-2 and X addressing means 11-1,11-2 of the serial access memory has substantially the same circuit construction and performs substantially the same circuit operation as conventional general-purpose memory circuits, for example, DRAM circuits, so that its further description is omitted. Using FIG. 2, the serial access means 20-1,20-2 in FIG. 1 will hereinafter be described in detail.
FIG. 2 is a circuit diagram of the serial access means 20-1,20-2 in FIG. 1.
The serial access means 20-1 has transfer means 21-1 to 21-1n which are connected to the plurality of paired bit lines BL1-1,BL1-1 to BL1-n,BL1-n of the memory matrix 10-1, respectively. The transfer means 21-11 to 21-1n are each composed of a pair of NMOS transistors. Describing in detail about the connection between the transfer means 21-11 and the paired bit lines BL1-1,BL1-1, a first electrode which is the source or drain of one of the NMOS transistors of the transfer means 21-11 is connected to one of the bit lines, i.e., the bit lines BL1-1 and a first electrode of the other NMOS transistor is connected to the other bit line BL1-1. The other transfer means is connected with its corresponding bit lines in a similar manner.
The gate electrodes of all the NMOS transistors of the transfer means 21-1 are commonly connected so that a signal Pt can be applied to all the gate electrodes practically at t
REFERENCES:
patent: 5193071 (1993-03-01), Umina et al.
Fears Terrell W.
Manzo Edward D.
OKI Electric Industry Co., Ltd.
Ringsred Ted K.
LandOfFree
Serial access memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Serial access memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Serial access memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-78546