Process for forming a planarized interlayer insulating film in a

Details Process for forming a planarized interlayer insulating film in a Process for forming a planarized interlayer insulating film in a

1994-11-17

1996-12-03

Fourson, George

Fishing, trapping, and vermin destroying

437228, 437229, H01L 2128

Patent

active

055808263

ABSTRACT:
In a process for manufacturing a semiconductor device, on a surface including interconnections selectively formed on an insulating film, an interlayer insulating film to have a thickness thicker than that of the interconnections is deposited. A positive type photoresist is deposited, and then, exposed through a mask having a regular stripe pattern extending over the whole of the mask, while causing an exposing light to focus on a low altitude region of the interlayer insulating film. The photoresist is developed, with the result that a regular pattern of the developed photoresist is formed on only a low altitude region. A second resist is deposited on a surface including the first resist so as to cause the second resist to have a substantially planarized surface. Then, an etch-back is performed for a whole surface at least until a surface of the low altitude region of the interlayer insulating film is exposed, whereby an upper surface of the interlayer insulating film is planarized.

REFERENCES:
patent: 5077234 (1991-12-01), Scoopo et al.
patent: 5212114 (1993-05-01), Grewal et al.
patent: 5292689 (1994-03-01), Cronin et al.
"A Four-Level-Metal Fully Planarized Interconnect Technology For Dense High Performance Logic and SRAM Applications"; Ronald R. Uttecht and Robert M. Geffken; IBM General Technology Division; 1991 VMIC Conference; p. 20.
"A New Interlayer Formation Technology For Completely Planarized Multilevel Interconnection by Using LPD"; T. Homma et al.; NEC Corporation; 1990 IEEE; 1990 Symposium on VLSI Technology; pp. 3 and 4.
"Two-Layer Planarization Process"; A. Schiltz and M. Pans; Centre National d'Etudes des Telecommunications, Zirst, Meyland, France; J. Electrochem. Soc.; vol. 133, No. 1; pp. 178-181 (Jan. 1986).
"A Planarization Technology Using a Bias-Deposited Dielectric film and an Etch-Back Process"; Shinji Fujii, et al.; IEEE Transactions on Electron Devices, vol. 35, No. 11, Nov. 1988; pp. 1829-1833.
"Application of a Two-layer Planarization Process to VLSI Intermetal Dielectric and Trench Isolation Processes"; D. J. Sheldon et al.; 1988 IEEE; pp. 140-146.
"A High Performance, Four Metal Layer Interconnect System for Bipolar and BICMOS Circuits"; S. R. Wilson et al.; Advanced Technology Center; Motorola Semiconductor Products Sector; 1990 VMIC Conference; pp. 42-47.

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