Switching technique for attaining synchronization

Details Switching technique for attaining synchronization Switching technique for attaining synchronization

1990-12-03

1992-08-04

Chin, Stephen

Pulse or digital communications

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331 1A, H04L 700

Patent

active

051366177

ABSTRACT:
Synchronization of a local clock in a transmission system node is achieved by using synchronization circuitry such as a phase-locked loop (PLL). This synchronization circuitry is provided with a selected one of a multiplicity of timing signals derived from incoming bit streams to the node. The selected timing signal is employed by the synchronization circuity as a reference timing signal to which the local clock is synchronized. The timing-signal selection is facilitated by a switch controlled by a process or to relay the timing signal, derived from the most desirable bit stream, to the synchronization circuitry. This processor determines such a bit stream based on various indicators of the signal quality thereof. Moreover, the switch operates at such a speed that the synchronization circuitry is precluded from free-running during any switching period.

REFERENCES:
patent: 4305045 (1981-12-01), Metz et al.
patent: 4633193 (1986-12-01), Scordo
patent: 4651103 (1987-03-01), Grimes
patent: 4736393 (1988-04-01), Grimes et al.
patent: 4926447 (1990-05-01), Corsetto et al.
patent: 4972442 (1990-11-01), Steierman
patent: 4980899 (1990-12-01), Troost et al.

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