Local oxidation process for high field threshold applications

Fishing – trapping – and vermin destroying

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437 69, 437 72, 437 73, 437247, H01L 2176

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055808166

ABSTRACT:
A method for electrically isolating semiconductor devices in an integrated circuit structure with high field threshold, low defect level regions. The semiconductor structure includes a device layer predominantly comprising lattice silicon with a surface suitable for device formation. Multiple device regions are defined and field regions are defined for electrically isolating the device regions from one another. Dopant species are implanted to create a channel stop adjacent two of the device regions. The implant is of sufficient energy and concentration to impart within the device layer nucleation sites of the type known to result in stacking faults during oxide growth conditions. A thickness of thermally grown silicon dioxide is formed in the field regions by first thermally processing the integrated circuit structure to remove nucleation sites from the device layer and form a minor portion of the field oxide thickness. Subsequently a major portion of the oxide thickness is formed under relatively fast growth conditions.

REFERENCES:
patent: 4472873 (1984-09-01), Ko
patent: 5110756 (1992-05-01), Gregor et al.
Excerpts from Silicon Processing for the VLSI Era by Wolf, et al.
Linn, et al "The Growth of Oxidation Stacking Faults and the Point Defect Generation at Si-SiO Interface during Thermal Oxidation of Silicon" from J. Electrochem Soc.: Solid-State Science and Technology, May 1981. Pp. 1121-1130.

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