Method of fabricating bipolar transistor having a guard ring

Details Method of fabricating bipolar transistor having a guard ring Method of fabricating bipolar transistor having a guard ring

1994-12-12

1996-12-03

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 31, 437 74, 437 76, 148DIG10, H01L 21265

Patent

active

055807984

ABSTRACT:
In a bipolar or BiCMOS process, a heavily doped buried layer of a first conductivity type and a heavily doped channel stop region of a second conductivity type are formed in a lightly doped substrate of the second conductivity type. A lightly doped epitaxial layer of the first conductivity type is grown. An implant of the first conductivity type creates a guard ring around the bipolar transistor active region and also creates a higher-doped collector region inside the active region. In the BiCMOS process, during the formation of CMOS wells, a silicon nitride mask over the bipolar transistor inhibits oxidation of the epitaxial layer and the oxidation-enhanced diffusion of the buried layer. As a result, the epitaxial layer can be made thinner, reducing the collector resistance. The MOS transistor wells can be formed without an underlying buried layer, simplifying the process and decoupling the bipolar and MOS transistor characteristics from each other. A heavy implant of the second conductivity type creates a field implant region around each transistor. Around the bipolar transistor, the field implant region meets the channel stop region. Field oxide is grown over the field implant region by LOCOS process. A base region is formed inside the guard ring. Other features and embodiments are described in the specification, the drawings and the claims.

REFERENCES:
patent: 3082269 (1976-09-01), Torreno, Jr. et al.
patent: 3982269 (1976-09-01), Torreno, Jr. et al.
patent: 4110126 (1978-08-01), Bergeron et al.
patent: 4404738 (1983-09-01), Sasaki et al.
patent: 4458158 (1984-07-01), Mayrand
patent: 4570328 (1986-02-01), Price et al.
patent: 4897709 (1990-01-01), Yokoyama et al.
patent: 4931411 (1990-06-01), Tigelaar
patent: 4933295 (1990-06-01), Feist
patent: 4943536 (1990-07-01), Havemann
patent: 4980020 (1990-12-01), Douglas
patent: 5059549 (1991-10-01), Furuhata
patent: 5094980 (1992-03-01), Shepela
patent: 5098854 (1992-03-01), Kapoor et al.
patent: 5100811 (1992-03-01), Winnerl et al.
patent: 5102811 (1992-04-01), Scott
patent: 5164331 (1992-11-01), Lin et al.
patent: 5166082 (1992-11-01), Nakamura et al.
patent: 5171702 (1992-12-01), Prengle et al.
patent: 5175118 (1992-12-01), Yoneda
patent: 5179031 (1993-01-01), Brassington et al.
patent: 5179036 (1993-01-01), Matsumoto
patent: 5218224 (1993-06-01), Taguchi
patent: 5219784 (1993-06-01), Solheim
patent: 5274267 (1993-12-01), Moksvold
Jong Ho Lee et al., "Under Field Oxide Dopant Enhancement (UFDE) For CMOS AMD BiCMOS Technology", Japanese Journal of Applied Physics, vol. 29 No. 12 (Dec. 1990), pp. 2292-2295.
Iranmanesh et al., "A 0.8-.mu.m Advanced Single-Poly BiCMOS Technology for High-Density and High-Performance Applications," IEEE Journal of Solid State Circuits, vol. 26, No. 3, Mar., 1991, pp. 422-426.
J. L. de Jong et al., "Single Polysilicon Layer Advanced Super High-speed BiCMOS Technology," Paper 7.4, IEEE, 1989, pp. 182-185.
A. Nouailhat et al., "Development of Advanced CMOS-Compatible Bipolar Transistor for BiCMOS Technology," Electronics Letters, vol. 24, No. 25, Dec. 8, 1988, pp. 1581-1983.
Stanley Wolf, "Silicon Processing for the VLSI Era," vol. 2, Process Integration, Lattice Press, 1990, pp. 13-44, 143-150, 162-169, 482-483, 486-502, 504, 505, 510-522, 532-535, 538-543 and 546-551.
U.S. Ser. No. 8/085,436, Grubisich, Jun. 30, 1993.
U.S. Ser. No. 8/202,328, Grubisich, Feb. 28, 1994.
U.S. Ser. No. 8/202,532, Grubisich, Feb. 28, 1994.
U.S. Ser. No. 8/085,436 Grubisich Jun. 30, 1993.
U.S. Ser. No. 8/202,328 Grubisich Feb. 28, 1994.
U.S. Ser. No. 8/202,532 Grubisich Feb. 28, 1994.

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