Semiconductor memory device transistor and cell structure

Details Semiconductor memory device transistor and cell structure Semiconductor memory device transistor and cell structure

1991-06-06

1992-02-11

James, Andrew J.

357 68, 357 51, H01L 2968, H01L 2978, H01L 2992

Patent

active

050879510

ABSTRACT:
A dymanic random access memory device is constructed in which a first layer of semiconductive material is used to form series of transistors, using buried contacts on a silicon substrate. A dielectric is formed over the surface, and memory cells include a second layer of semiconductive material which is deposited over a dielectric. The active regions of the DRAM form a "dogbone" pattern, in which active regions exhibit elongate shapes in which each end of the elongate shape is wider than a center leg, and adjacent "dogbone" shapes are nested to form a compact pattern.

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