Fishing – trapping – and vermin destroying
Patent
1989-06-23
1991-06-11
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437229, 437235, 148DIG51, 156644, 1566591, 1566611, H01L 2100, H01L 2102, H01L 21302, H01L 21314
Patent
active
050232037
ABSTRACT:
A method for reducing the line widths produced by patterning a semiconduc substrate with a multilayer resist mask employs a `spacer`-forming oxide layer which is non-selectively formed over the mask structure after an aperture for exposing a lower resist layer has been formed in an upper portion of the multilayer mask, but prior to etching a lower resist layer. The oxide layer is subjected to a dry systemic etch to vertically remove material of the oxide layer down to the surface of the lower resist layer. Because of the substantial step coverage of the oxide layer, a `spacer` or `stringer` portion remains along the sidewalls of the original aperture in the upper portion of the mask, whereby the dimensions of the exposure window are reduced. Retaining this sidewall spacer as an integral part of mask structure permits narrower line widths to be replicated in the underlying substrate.
REFERENCES:
patent: 4351894 (1982-09-01), Yonezawa et al.
patent: 4373965 (1983-02-01), Smigelski
patent: 4412378 (1983-11-01), Shinada
patent: 4432132 (1984-02-01), Kinsbron et al.
patent: 4455742 (1984-06-01), Williams et al.
Everhart B.
Hearn Brian E.
Korea Electronics & Telecommunications Research Institute et al.
LandOfFree
Method of patterning fine line width semiconductor topology usin does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of patterning fine line width semiconductor topology usin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of patterning fine line width semiconductor topology usin will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-782497