Method of forming vertical FET device with low gate to source ov

Details Method of forming vertical FET device with low gate to source ov Method of forming vertical FET device with low gate to source ov

1990-10-31

1992-02-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437 49, 437913, 437915, H01L 21265

Patent

active

050875817

ABSTRACT:
This is a vertical MOSFET device with low gate to source overlap capacitance. It can comprise a semiconductor substrate 22 of the first conductivity type, a source region 24, 26 of a second conductivity type formed in the upper surface of the substrate 22; a vertical pillar with a channel region 28 of the first conductivity type, a lightly doped drain region 30 of the second conductivity type and a highly doped drain contact region 32 of the second conductivity type; a gate insulator 34, a gate electrode 36 surrounding the vertical pillar, and an insulating spacer 38 between the source 24, 26 and a portion of the gate 36 regions. This is also a method of forming a vertical MOSFET device on a single crystal semiconductor substrate, with the device having a pillar on the substrate, with the pillar having a channel region in a lower portion and with the channel region having a top and a highly doped first source/drain region in an upper portion of the pillar, with the substrate having a highly doped second source/drain region and with a gate insulator on the substrate and on the pillar. The method comprises: isotropically forming a first gate electrode material layer on the pillar and the substrate; anisotropically etching the first gate electrode material leaving a vertical portion of gate electrode material on the pillar; anisotropically depositing an insulating spacer; and conformally depositing a second gate electrode material layer.

REFERENCES:
patent: 3761785 (1973-09-01), Prunioux
patent: 4449285 (1984-05-01), Janes et al.
patent: 4630088 (1986-12-01), Ogura et al.
patent: 4670768 (1987-06-01), Sunami et al.
patent: 4960723 (1990-10-01), Davies

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