Multiplier for binary numbers comprising a very high number of b

Details Multiplier for binary numbers comprising a very high number of b Multiplier for binary numbers comprising a very high number of b

1989-02-15

1990-11-13

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 752

Patent

active

049706756

ABSTRACT:
A multiplier for two binary values, X and Y, comprising a very high number (q) of bits, wherein memories storing the numbers X and Y and a result register MR are provided, X being expressed as the sequence of bits (x.sub.q-1 . . . x.sub.j . . . x.sub.0), uses the algorithm consisting in sequentially carrying out from j=q-1 to j=0 the additions 2R+x.sub.j Y and each time entering the result in the result memory (MR). In this multiplier the adders are grouped into n blocks of m bits (with n.times.m=q), m being chosen so that the carry transfer time into a block is lower than a clock period. Each block comprises a first and a second line of elementary adders forming the cells (C.sub.1 to C.sub.m+1) associated with each pair of bits to be added. This multiplier is more particularly adapted for carrying out the operations XYmodN and X.sup.S modN.

REFERENCES:
patent: 3098153 (1963-07-01), Heijn
L. De Vos et al., "A Fast Adder-Based Multiplication Unit For Customised Digital Signal Processors" ICASSP 86, Tokyo (Apr. 1986): 2163-2166.

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