Exception handling in a pipelined microprocessor

Details Exception handling in a pipelined microprocessor Exception handling in a pipelined microprocessor

1989-04-26

1990-11-13

Fleming, Michael R.

Boots, shoes, and leggings

G06F 1210

Patent

active

049706411

ABSTRACT:
A method for processing address translation exceptions occurring in a virtual memory system employing demand paging and having a plurality of registers and a real storage area, includes the steps of: (a) temporarily storing for each storage operation; (i) the effective storage address for the operation; (ii) exception control word information relative to the ones of the registers involved in the operation and the length and type of the operation; and (iii) any data to be stored during the operation; (b) retrieving the temporarily stored information to form an exception status block if an exception is generated indicating a failed operation; and (c) reinitiating the failed operation based on the information contained in the exception status block.

REFERENCES:
patent: 3921153 (1975-11-01), Belady et al.
patent: 3947823 (1976-03-01), Padegs et al.
patent: 4110822 (1978-08-01), Porter et al.
patent: 4613935 (1986-09-01), Couleur

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