Bank switchable memory system

Details Bank switchable memory system Bank switchable memory system

Filed on

1981-05-07

Date issued

1983-01-11

Examiner

Ruggiero, Joseph F.

Patent Class

Boots, shoes, and leggings

Other Related Categories

G06F 930

Type

Patent

Status

active

Patent number

043685153

Description

ABSTRACT:
A decoding circuit is coupled to the signal lines that communicate address signals to a memory unit. When a predetermined address is communicated, the decoding circuit produces a supplemental signal that is coupled to the memory unit and used to select one of a plurality of groups of memory locations. The communicated address signals specify the memory location of the selected group to be accessed.

REFERENCES:
patent: 3737860 (1973-06-01), Sporer
patent: 3781812 (1973-12-01), Wymore et al.
patent: 4042911 (1977-08-01), Bourke et al.
patent: 4064554 (1977-12-01), Tubbs
patent: 4118773 (1978-10-01), Raguin et al.
patent: 4145745 (1979-03-01), De Bijl et al.
patent: 4149239 (1979-04-01), Jenkins et al.
patent: 4158227 (1979-06-01), Baxter et al.
patent: 4181933 (1980-01-01), Benysek
Poppendieck, M. et al., "Memory Extension Techniques for Minicomputers," Computer, May 1977, pp. 68-75.

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