Partial roll mode transfer for cyclic bulk memory

Details Partial roll mode transfer for cyclic bulk memory Partial roll mode transfer for cyclic bulk memory

1980-03-24

1983-01-11

Nusbaum, Mark E.

Boots, shoes, and leggings

G06F 722

Patent

active

043685137

ABSTRACT:
Latency of a cyclic bulk storage device attached to a CPU and a main storage through standard channel facilities is reduced without modification of the channel and CPU hardwares. The storage device is divided into a plurality of randomly accessible pages each having parallel cyclic tracks. Each page is subdivided into two sequentially and cyclically accessible Sectors 0 and Sector 1. Parallel bits on different tracks form bytes. Data are transferred byte by byte between a selected page of the device and a specified one-page data area in the main storage. A channel program is constructed using three commands (CCWs); a Seek Page command followed by two different Read or Write commands. At the end of the Seek Page operation, a control unit determines which of Sector 0 or 1 is more immediately accessible. If it is Sector 0 a branching control signal given to the channel causes the channel to chain to the second CCW, but if it is Sector 1, a different control signal given to the channel causes it to skip over the second CCW and chain to the third CCW. When chained to the second CCW, the channel executes the transfer of one page of data in normal sequence, i.e. Sector 0 first and Sector 1 next. When chained to the third CCW, the channel executes the data transfer in reverse sequence, i.e. Sector 1 first and Sector 0 next. Such sector transfers are selectively controlled by indirect data address words (IDAWs).

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