Method of fabricating a high density EPROM cell on a trench wall

Details Method of fabricating a high density EPROM cell on a trench wall Method of fabricating a high density EPROM cell on a trench wall

1991-05-20

1992-08-04

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 63, 148DIG50, 148DIG168, H01L 21304

Patent

active

051358794

ABSTRACT:
One embodiment of the present invention provides an EPROM array having floating gate field effect transistors formed on the sidewalls of trenches formed in a semiconducting substrate. Simultaneous with the fabrication of these trench wall transistors, column lines are formed between the trenches to the top surface and in the bottom of the trenches which extend from one end to the other of the memory array.

REFERENCES:
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patent: 4169291 (1979-09-01), Rossler
patent: 4194283 (1980-03-01), Hoffman
patent: 4206005 (1980-06-01), Yeh
patent: 4222062 (1980-09-01), Trotter et al.
patent: 4326332 (1982-04-01), Kenney
patent: 4353082 (1982-10-01), Chatterjee
patent: 4364074 (1982-12-01), Garnache et al.
patent: 4493740 (1985-01-01), Komeda
patent: 4542396 (1985-09-01), Schutten et al.
Kenney, "Self-Aligned U-Groove Gates for Field-Effect Transistors", IBM TBB, vol. 22, No. 10, pp. 4448-4449, Mar. 1980.

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