Method of making high voltage vertical field effect transistor w

Details Method of making high voltage vertical field effect transistor w Method of making high voltage vertical field effect transistor w

1990-03-02

1990-11-13

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 40, 437 41, 437235, 437247, 357 234, H01L 21265

Patent

active

049701738

ABSTRACT:
A vertical field effect transistor having a first low resistivity region which determines breakdown voltage and a second low resistively region which is formed underneath a portion of a source is provided. The second low resistivity region lowers the gain of a parasitic bipolar transistor, and lowers resistance of a base region under the source of the field effect transistor, improving the commutating safe operating area of the vertical field effect transistor.

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Mutsushio et al.; "An Isolated Gate Bipolar Transistor with aligned DMOS Structure", IEDM 88-813, 1988.
Matsuhio Mori et al., "An Isolated Gate Bipolar Transistor with Self-Aligned DMOS Structure IEDM", 1988, pp. 813-816.

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