Methods and computer programs for minimizing logic circuit desig

Details Methods and computer programs for minimizing logic circuit desig Methods and computer programs for minimizing logic circuit desig

1997-09-25

1999-10-26

Teska, Kevin

39550004, G06F 1750

Patent

active

059742429

ABSTRACT:
Methods and computer programs for logic circuit design minimization with Identity cell representation is provided which can simplify logic circuit design by combining and minimizing Identity cells and thereby reducing the number of gates in the logic circuit. All possible Identity cells from a given logic function are generated by combining every possible pair of logic terms, then equivalent Identity cell terms are eliminated and the best subset of Identity cell terms which covers all the minterms of the given logic function is provided.
The I-cell term representation is sufficiently broad in its scope to allow representation of sub-functions such as ABC+ABC as a single entity that can be readily used for minimization which may be advantageously used in logic circuit fabrication and design. Since I-cell representation includes sum of products, EXOR, EXNOR and other logic terms, fewer terms will be needed to represent a given Boolean function, and a much more simplified, inexpensive and advantageous optimal logic design structure will be obtained.

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