Modular multiplication method and the system for processing data

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364754, G06F 738

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active

051445743

ABSTRACT:
To markedly improve the computational speed of A.times.B modulo N computation as compared with the prior-art Baker's method where A denotes a multiplicand; B denotes a multiplier; and N denotes a modulus, the number of multiply-additions and division (modular) substractions is reduced on the basis of any given same higher radix number r. In practice, the modular subtracters c(k)N are previously determined on the basis of the partial products b(k-1)A at the succeeding processing stage (k-1) to reduce the absolute value of the partial remainder R(k) down to a value less than a modulus N, so that bit overflow from a predetermined computational range can be prevented. For instance, when the partial product b(k)A at the succeeding processing stage (k-1) is large, the modular subtracter c(k)N at the current stage (k) is also determined large. Further, the most significant bit of the multiplicand A is eliminated by transforming the multiplicand A from a range within [0, N-1] to a range [-N/2, N/2] to reduce the absolute value of the partial product. This is necessary to apply the same radix number r to both the partial products and the modular subtracters.

REFERENCES:
patent: 4346451 (1982-08-01), Katayama
patent: 4366549 (1982-08-01), Katayama
"On a Fast Iterative Multiplication Method by Recording Imtermediate Products," by Takagi (undated), A translation accompanies original Japanese doc.
Computer Arithmetic, by Kai Hwang, Chapter 7: Standard and High-Radix Dividers (pp. 213-221); John Wiley & Sons, 1979.

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