Method and apparatus for providing flow control with lying for i

Details Method and apparatus for providing flow control with lying for i Method and apparatus for providing flow control with lying for i

1995-05-15

1997-06-10

Treat, William M.

395877, 395854, 395821, G06F 1200

Patent

active

056385358

ABSTRACT:
A flow control circuit for a computer system including a first-in first-out buffer including a register for storing a value indicating the number of stages of the FIFO which are available to store data, circuitry for detecting whether an input/output device is able to process data more rapidly than the FIFO is emptied, and circuitry for providing an value greater than the number of stages actually available for storage in the FIFO if the input/output device is able to process data more rapidly than the FIFO is emptied.

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patent: 5313620 (1994-05-01), Cohen et al.
patent: 5440691 (1995-08-01), Carrafiello et al.
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patent: 5473756 (1995-12-01), Traylor
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patent: 5546543 (1996-08-01), Yang et al.
patent: 5557750 (1996-09-01), Moore et al.
BIST for ring-address SRAM-type FIFOs by Goor et al., 1994 IEEE publication, pp. 112-118. 1994.

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