Phase detection circuit for stepwise measurement of a phase rela

Details Phase detection circuit for stepwise measurement of a phase rela Phase detection circuit for stepwise measurement of a phase rela

1989-06-21

1990-10-23

Olms, Douglas W.

Pulse or digital communications

Spread spectrum

Direct sequence

331 96, 328 55, 328 72, H04L 700

Patent

active

049658158

ABSTRACT:
In a phase detection circuit for detecting the phase relation between a first (f.sub.1) and a second (f.sub.2) clock signal in which tappings (b, c, d, e, f, g, h, i) of a delay circuit (7) for the first clock signal are connected to memory elements (27, 29, 31, 33, 35, 37, 39, 41) clocked by the second clock signal and having their outputs (B, C, D, E, F, G, H, I) connected to a logic circuit (59) and in which a plurality of outputs of the delay circuit (7) is connected to a measuring circuit (89, 95) for measuring the delay time of the delay circuit, a control circuit (87, 85, 93, 91, 83, 77, 79, 81) controlled by the measuring circuit is arranged for controlling the delay time of the delay circuit at a value corresponding to the period of the first clock signal, while the logic circuit includes an AND-gate (61, 65, 69, 73) alternating with a NOR-gate (63, 67, 71, 75) for obtaining a very accurate and unambiguous phase detection, using few circuit elements.

REFERENCES:
patent: 4584695 (1986-04-01), Wong et al.
patent: 4604582 (1986-08-01), Strenkowski et al.
patent: 4713621 (1987-12-01), Nakamura et al.
IDTV Receiver, Kawai et al; IEEE Transactions on Consumer Electronics, vol. CE--33, No. 3, Aug. 1987.

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