Method and apparatus for transmitting and receiving data at both

Details Method and apparatus for transmitting and receiving data at both Method and apparatus for transmitting and receiving data at both

1997-08-22

1999-10-26

Mai, Son

Static information storage and retrieval

Addressing

Sync/clocking

36518905, G11C 800

Patent

active

059739894

ABSTRACT:
A synchronous memory circuit having a memory array and a control circuit. The control circuit is responsive to a clock signal having a rising edge and a falling edge. The control circuit generates control signals for accessing the memory array at the rising edge and the falling edge of the clock signal. A read circuit is responsive to the control signals and generates read data signals indicative of data stored in the memory array. A write circuit is responsive to the control signals and stores data in the memory array.

REFERENCES:
patent: 5226011 (1993-07-01), Yanagisawa
patent: 5390149 (1995-02-01), Vogley et al.
patent: 5416739 (1995-05-01), Wong
patent: 5726950 (1998-03-01), Okamoto

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