Nonvolatile semiconductor memory

Static information storage and retrieval – Floating gate – Particular biasing

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36523006, G11C 1600

Patent

active

059739630

ABSTRACT:
There is provided a nonvolatile semiconductor memory which can simplify a circuit structure of a row decoder circuit to minimize an increase in chip size, and selectively supply a negative voltage to a word line. The nonvolatile semiconductor memory has a row decoder circuit section for selecting one of word lines in a memory cell array in response to an input address, and outputting a negative voltage or high voltage to the selected word line in accordance with a selected mode while outputting a ground potential to non-selected word lines. In such a nonvolatile semiconductor memory, each of predecoders comprises supply voltage-high voltage and ground-negative voltage converting circuits for converting the output levels into levels of supply voltage-high voltage and ground-negative voltage respectively in response to the input address, high-voltage and negative-voltage drivers for outputting from the first and second terminals the high voltage or the negative voltage in accordance with each output from these converting circuits, and a select address driver for outputting a voltage activated by the outputs of the voltage drivers and switched by the selected mode.

REFERENCES:
patent: 5265052 (1993-11-01), D'Arrigo et al.
patent: 5287536 (1994-02-01), Schreck et al.
patent: 5365479 (1994-11-01), Hoang et al.
patent: 5396459 (1995-03-01), Arakawa
patent: 5455789 (1995-10-01), Nakamura
patent: 5661683 (1997-08-01), Song

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