Saturable charge FET

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357 16, 357 58, H01L 2980

Patent

active

049656457

ABSTRACT:
A new gallium arsenide gate heterojunction FET is disclosed. The gate is a multi-layer structure including an intermediate carrier depletable layer. Upon applying a gate voltage, the intermediate layer becomes depleted thereby effectively increasing the gate resistance and reducing gate leakage current.

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T. Zipperian et al., "A GaAs/InGaAs/GaAs . . . FET," Inst. Phys. Conf. Ser. No. 79, Ch. 8, Int. Symp. GaAs and Related Compounds, Karuizawa, Japan 1985, pp. 421-425.
P. M. Solomon, et al., "A GaAs Gate Heterojunction FET", IEEE Electron Device Letters, vol. EDL-5, No. 9, Sep. 1984.
H. Kinoshita, et al., "A New Insulated Gate Inverted Structure Modulation Doped AlGaAs/GaAs/N-AlGaAs FET", Jap. J. App. Phys., vol. 23, p. L836, 1924.
M. Ogura, et al., "Self Aligned Enhancement Mode FET with AlGaAs as Gate Insulator", Journal of Vacuum Science & Technology B, vol. 3, p. 581, 1985.

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