Method for eliminating a false critical path in a logic circuit

Details Method for eliminating a false critical path in a logic circuit Method for eliminating a false critical path in a logic circuit

1995-04-06

1997-06-10

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364490, 364580, 371 222, 371 251, 371 28, 29847, 29850, G06F 1500, G01R 3128

Patent

active

056382901

ABSTRACT:
A method for removing the critical false paths takes place during logic optimization. It is based on a path-constrained redundancy removal algorithm. This path-constrained redundancy removal algorithm automatically finds that a path node does not affect the behavior of the path output and so determines a critical path. This method is iteratively repeated for as long as this critical path is false.

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