Self latching input buffer

Details Self latching input buffer Self latching input buffer

1991-11-26

1992-09-01

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307481, H03K 190175, H03K 096

Patent

active

051441683

ABSTRACT:
A self latching input buffer is disclosed which includes an address input buffer which is responsive to a first clock signal so as to produce an output signal. Data in the input buffer is latched in connection with the receipt of a second clock signal which is produced by a detector which is responsive to the output signal.

REFERENCES:
patent: 4436791 (1984-03-01), Gingerich
patent: 4451745 (1984-05-01), Itoh et al.
patent: 4458337 (1984-07-01), Takemae et al.
patent: 4825420 (1989-04-01), Min
patent: 4951258 (1990-08-01), Uehara
patent: 4970694 (1990-11-01), Tanaka et al.
patent: 4985868 (1991-01-01), Nakano et al.
patent: 4986666 (1991-01-01), Homma et al.
patent: 5003513 (1991-03-01), Porter et al.

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