Obtaining accurate on-chip time-constants and conductances

Details Obtaining accurate on-chip time-constants and conductances Obtaining accurate on-chip time-constants and conductances

1998-03-25

1999-10-26

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327158, 307 39, H03L 706

Patent

active

059735244

ABSTRACT:
A bias circuit for obtaining accurate on-chip time constants and resistances. The bias circuit includes a constant-g.sub.m bias circuit and feedback loop circuit. The constant-g.sub.m bias circuit has a mos transistor device and a variable resistor device which are arranged so that the trandsconductance of the transistor device is dependent upon the resistance of the resistor device. The constant-g.sub.m bias circuit generates a bias output signal that is a function of the trandsconductance of the transistor device. The feedback loop circuit includes signal generation means responsive to the bias output signal for generating a signal that is a function of the bias signal. The loop circuit further includes a comparison means for comparing the generated signal to a known external frequency reference, and an output that is operatively connected to the variable resistor device for adjusting the value of the variable resistor device until the generated signal matches the external reference signal. Also provided is a variable resistor device for use in a loop circuit (including the present bias circuit). The resistor device includes an analog-controlled resistor device and a digitally-controlled resistor device. The analog-controlled resistor device is adjusted in response to variations occurring in a control signal between a maximum voltage and a minimal voltage. The digitally-controlled resistor is adjusted in discrete steps whenever the control voltage reaches the maximum or minimum voltage, after which the control voltage is forced to a value approximately half-way between the minimum and maximum voltage.

REFERENCES:
patent: 5070332 (1991-12-01), Kaller et al.
patent: 5223743 (1993-06-01), Nakagawara
patent: 5585754 (1996-12-01), Yamashina et al.
J.M. Steiniger, "Uderstanding Wide-band MOS Transistors", IEEE Circuits and Devices, vol. 6, No. 3, pp. 26-31, May 1990.
J. Ryan et al, "A Magnetic Field Sensitive Amplifier with Temperature Compensation", ISSCC Digest of Technical Papers, pp. 124-125, Feb. 1992.
T. H. Lee, "The Design of CMOS Radio-Frequency Itegrated Circuits", Cambridge University Press, pp. 235-237, 1998.
D.J. Johns and K. Martin, "Analog Integrated Circuits Design", John Wiley & Sons, Inc., pp. 248-250, 256-260, 1997.
W. Chan et al, "A 622 --MHz Interpolating Ring VCO with Temperature Compensation and Jitter Analysis", 1997 International Synopsium on Circuits & Systems, pp. 25-28, Jun. 1997.

Affiliated with

Also associated with

Rating

Obtaining accurate on-chip time-constants and conductances does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Obtaining accurate on-chip time-constants and conductances, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Obtaining accurate on-chip time-constants and conductances will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-768902