Unitary multiplexer-decoder circuit

Details Unitary multiplexer-decoder circuit Unitary multiplexer-decoder circuit

1984-07-09

1986-09-23

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307467, 307297, 323283, 323313, H03K 19013, H03K 19086, H03K 1920, G05F 322

Patent

active

046137742

ABSTRACT:
A unitary multiplexer-decoder circuit integrated on a single semiconductor chip includes a first reference transistor, a plurality of first data input transistors, a second reference transistor, a plurality of second data input transistors, an emitter follower, a first current source and a second current source. A reference voltage generator is provided for generating first and second reference potentials and is formed on the same integrated circuit substrate as the multiplexer-decoder circuit.

REFERENCES:
patent: 3539824 (1970-11-01), Yu et al.
patent: 4348747 (1982-09-01), Takahashi
patent: 4354266 (1982-10-01), Cooperman
patent: 4551638 (1985-11-01), Varadarajan
Gersbach et al, "Cascode Decoder", IBM TDB; vol. 8, No. 4, pp. 642-643; 9/1965.
Gosch, "Bipolar Multiplexer Can Reach 2Gb/s"; Electronics; p. 96; 10/6/1983.

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