Spacer isolation method for minimizing parasitic sidewall capaci

Details Spacer isolation method for minimizing parasitic sidewall capaci Spacer isolation method for minimizing parasitic sidewall capaci

1989-03-15

1990-10-23

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 67, 437 69, 437 72, H01L 2176

Patent

active

049652214

ABSTRACT:
A modification of the LOCal Oxidation of Silicon (LOCOS) isolation process, whereby prior to the oxidation of silicon substrate that is exposed upon etching the protective CVD nitride layer, a conformal layer of CVD oxide is deposited on the surface of the array. Following an anisotropic etch of the conformal layer, a portion of the conformal layer remains about the peripheries of the etched apertures within the nitride layer. These "spacers" will serve as an anti-encroachment device during field oxide growth and physically offset a subsequent silicon etch. Following a potassium hydroxide etch, which creates sloped-wall trenches in the array regions where silicon substrate is unprotected, the array receives a field implant. The spacers prevent the implanting of the channel-stop impurity near the active areas. Following the implant process, the array is subjected to a wet oxidation process which grows the field oxide regions. Oxide growth is allowed to proceed until the oxide thickness is approximately triple the original depth of the trenches. Following the wet oxidation, the field oxide is etched back with dilute hydrofluoric acid to the point where the upper surface of the field oxide is coplanar with the active areas. This modified LOCOS process provides fully-recessed field oxide regions, dramatically reduces the size of the bird's beak region, and virtually eliminates the problem of channel-stop implant encroachment.

REFERENCES:
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patent: 4472240 (1984-09-01), Kameyama
patent: 4538343 (1985-09-01), Pollack
patent: 4845048 (1989-07-01), Tamaki
patent: 4923563 (1990-05-01), Lee

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