Method for the manufacturing of insulated gate field effect tran

Details Method for the manufacturing of insulated gate field effect tran Method for the manufacturing of insulated gate field effect tran

1990-01-19

1990-10-23

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 89, 437241, 437 44, 357 233, H01L 21335

Patent

active

049652192

ABSTRACT:
The method involves the formation above the substrate of regions of epitaxial type automatically aligned with the gate electrode and designed to form the source and drain regions of the transistor. These regions are doped by ion implantation using a comparatively low implantation energy such that the doping agent does not penetrate into the substrate. By providing the source and drain junctions on the surface of the substrate, rather than in the substrate, there are no lateral junction capacitances and the horizontal dimensions of the IGFET may be reduced, with the result that high response speeds and high integration densities are obtained.

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Wong et al "Elevated Source/Drain MOSFET" IEDM Technical Digest pp. 634-637. 12/84.
Ghandhi, S. K. "VLSI Fabrication Principles" 1983 pp. 214-215, 242-245.

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