Method of making improved twin wells for CMOS devices by control

Details Method of making improved twin wells for CMOS devices by control Method of making improved twin wells for CMOS devices by control

1984-03-27

1985-05-14

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 295763, 148 15, 148187, 148DIG82, 156643, 357 42, 357 91, H01L 21265, H01L 2122, H01L 1700

Patent

active

045163162

ABSTRACT:
An improved method for forming complementary wells in a substrate is disclosed. A polysilicon layer is applied to the substrate, and the polysilicon layer is doped. An oxidation barrier layer is applied over the doped polysilicon layer. A portion of the doped polysilicon and oxidation layers are removed to expose a well region of one conductivity type in the substrate, and the well is then implanted in the exposed region. The surface of the well, and the polysilicon layer proximate the well beneath the oxidation barrier layer, are then steam oxidized until the lateral desired oxide penetration into the polysilicon layer beneath the oxidation barrier layer has been reached. This forms an oxide masking layer covering and extending beyond the formed well. The remaining oxide barrier layer is then removed to expose a well region of the other conductivity type. This second well region is spaced from the well region already formed by the extended oxide masking layer. The second well is then implanted. With the complementary wells implanted, the oxide masking layer is removed, and the wells are driven to the desired depth.

REFERENCES:
patent: 4295266 (1981-10-01), Hsu
patent: 4373965 (1983-02-01), Smigelski
patent: 4435895 (1984-03-01), Parrillo et al.
patent: 4441246 (1984-04-01), Redwine
patent: 4472459 (1984-09-01), Fisher

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