Method of forming a stacked capacitor using sidewall spacers and

Details Method of forming a stacked capacitor using sidewall spacers and Method of forming a stacked capacitor using sidewall spacers and

1994-10-05

1995-07-04

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2100

Patent

active

054299802

ABSTRACT:
A method for fabricating a capacitors on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a field effect transistor (FET), having one capacitor aligned over and contacting the source/drain of the FET in the device region. The capacitor is increased in capacitance by forming a double recess in the bottom electrodes of the storage capacitors. The method of forming the double recess utilizes a sidewall spacer and local oxidation technique. After forming the bottom electrode having the double recess an insulating layer having a high dielectric constant is deposited as the inter-electrode insulator and a stop electrode is formed, completing the storage capacitor and the dynamic random access memory (DRAM) storage cell.

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"A Newly Designed Planar Stacked Capacitor Cell with High Dielectric Constant Film for 256 Mbit DRAM" by T. Eimori et al. IEEE International Electron Device Meeting Proceedings, Dec. 1993, pp. 631-634.

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