Fishing – trapping – and vermin destroying
Patent
1994-10-03
1995-07-04
Thomas, Tom
Fishing, trapping, and vermin destroying
437 48, 437 52, H01L 218247
Patent
active
054299713
ABSTRACT:
A semiconductor transistor device on a semiconductor substrate comprises source/drain regions in the substrate. A tunnelling oxide layer combined with a gate oxide layer covers the substrate including the heavily doped regions. A pair of floating gates above the tunnelling oxide layer form source/drain relationships with three centrally located ones of the heavily doped regions. A first dielectric layer covers the floating gates. A set of control gates cover the first dielectric layer. A second dielectric layer covers the control gates. The floating gate structure, the first dielectric layer, the control gate layer and the second dielectric layer all forming with the three centrally located heavily doped regions an adjacent pair of stacked EEPROM transistor structures, with two additional, adjacent, outboard heavily doped regions. Spacers cover the tunneling oxide regions covering the second dielectric layer and the sides of the stacked structure, and a select gate line extends over the top of the spacer layer structure and in source/drain relationship with the two additional outboard heavily doped regions and the outer ones of the three centrally located heavily doped regions.
REFERENCES:
patent: 4420871 (1983-12-01), Schiebe
patent: 4950068 (1990-07-01), Sugaya
patent: 5081054 (1992-01-01), Wu et al.
Saile George O.
Thomas Tom
United Microelectronics Corporation
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