Process for forming twin well CMOS integrated circuits

Details Process for forming twin well CMOS integrated circuits Process for forming twin well CMOS integrated circuits

1993-06-22

1995-07-04

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437 41, 437 56, 437190, 148DIG82, H01L 218238

Patent

active

054299586

ABSTRACT:
A process of forming complementary insulated gate field effect transistors includes forming first and second well regions of first and second conductivity types in a planar semiconductor layer so that the well regions have an impurity retrograde impurity distribution profile. An insulator layer is then selectively formed with a first relatively thick insulator portion and thin gate portions. The first and second gates are formed on the relatively thin portions of the insulator layer. Insulator spacers are formed so as to extend laterally from the gates and from the relatively thick insulator portion. First impurities are introduced using the first gate and spacers as a mask to form first source and drain regions. Second impurities of an opposite conductivity type are introduced using the second gate and spacers as a mask to form source and drain regions of a complementary device.

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Rung et al., "A Retrograde p-Well for Higher Density CMOS", IEEE Trans. on Elect. Dev., vol. ED-28, No. 10, Oct. 1981, pp. 1115-1119.

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