Method and apparatus for parallel prediction and computation of

Details Method and apparatus for parallel prediction and computation of Method and apparatus for parallel prediction and computation of

1996-10-17

1999-09-21

Moise, Emmanuel L.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 738

Patent

active

059547901

ABSTRACT:
A floating point subtraction is performed on a first and second floating point number to obtain an exponent result and a fraction result, the first floating point number has a first exponent and a first fraction and the second floating point number has a second exponent and a second fraction. A first adder determines an exponent difference between the first and second exponents and, concurrently with determining the exponent difference, a prediction circuit predicts a massive cancellation prediction and a second adder determines the difference between the first and second fraction and generates a massive cancellation fraction result. Then it is determined whether the massive cancellation result is valid and if so, the massive cancellation fraction result is selected as a basis for the fraction result. If not, a result from the no massive cancellation path is selected as the basis for the fraction result.

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Hennessy & Patterson, "Computer Architecture: A Quantitative Approach", Morgan Kaufmann Publishers, Inc., San Mateo Ca, 1990, pp. A-18 to A-19.

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