Pyramid carry adder circuit

Details Pyramid carry adder circuit Pyramid carry adder circuit

1984-04-03

1987-04-21

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

046601651

ABSTRACT:
A digital adder circuit using principles similar to a pyramid carry adder, but with the ability to assimilate intermediate carry bits more rapidly. The circuit includes at least one adder stage for receiving multiple intermediate sum bits and multiple intermediate carry bits as inputs, and reducing the number of carry bits by a factor of at least three. The adder stage as disclosed is implemented in the form of current-mode logic. Preferably, a first adder stage includes multiple two-bit adder circuits, also in the form of current-mode logic, each two-bit adder circuit producing as outputs two sum bits and a carry bit.

REFERENCES:
patent: 3566098 (1970-02-01), Kono
patent: 3697735 (1972-10-01), Hanson
patent: 3700875 (1972-10-01), Saenger et al.
patent: 3925652 (1975-12-01), Miller
Willette et al, "Binary Adder" IBM Tech. Disclosure Bulletin, vol. 6, No. 4 Sep. 1963, pp. 39-40.
Wade, "Binary Adder with Quaternary Lookahead", IBM Tech. Disclosure Bulletin, vol. 7, No. 11, Apr. 1965, pp. 1006-1008.

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