High speed logic flip-flop latching arrangements including input

Details High speed logic flip-flop latching arrangements including input High speed logic flip-flop latching arrangements including input

1982-05-26

1985-03-19

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307272A, 377117, H03K 3356, H03K 2330, H03K 19017

Patent

active

045061670

ABSTRACT:
A high speed logic latching circuit consists of a pair of inverters and feedback switches used to latch the inverters. A pair of input switching means allows data to enter the latch when the latch is disabled. This configuration allows for high speed, reduced substrate area and true complementary outputs.

REFERENCES:
patent: 3577166 (1971-05-01), Yung
patent: 3812384 (1974-05-01), Skorup
patent: 3930169 (1975-12-01), Kuhn, Jr.
patent: 4096401 (1978-06-01), Hollingsworth
patent: 4107556 (1978-08-01), Stewart et al.
patent: 4138613 (1979-02-01), Tanaka
patent: 4181862 (1980-01-01), Dingwall
patent: 4182961 (1980-01-01), Dingwall
patent: 4300060 (1981-11-01), Yu

Affiliated with

Also associated with

Rating

High speed logic flip-flop latching arrangements including input does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed logic flip-flop latching arrangements including input, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed logic flip-flop latching arrangements including input will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-754840