Distributed multiport memory architecture

Details Distributed multiport memory architecture Distributed multiport memory architecture

1981-04-29

1983-07-19

Springborn, Harvey E.

Boots, shoes, and leggings

364900, G06F 922, G06F 1300

Patent

active

043947263

ABSTRACT:
A multiport memory architecture is disclosed for each of a plurality of task centers (11, 20, 30, 40) connected to a command and data bus (10). Each task center, (such as the center 11) includes a memory (13) and a plurality of devices (12, 14, 15, 17) which request direct memory access as needed. The memory (13) includes an internal data bus (53) and an internal address bus (50) to which the devices are connected, and direct timing and control logic (54) comprised of a 10-state ring counter (62) for allocating memory devices by enabling AND gates (64) connected to the request signal lines of the devices. The outputs of AND gates connected to the same device are combined by OR gates (66) to form an acknowledgement signal that enables the devices to address the memory during the next clock period. The length of the ring counter may be effectively lengthened to any multiple of ten to allow for more direct memory access intervals in one repetitive sequence. One device is a network bus adapter (14) which serially shifts onto the command and data bus (10) a data word (8 bits plus control and parity bits) during the next ten direct memory access intervals after it has been granted access. The NBA is therefore allocated only one access in every ten intervals, which is a predetermined interval for all centers. The ring counters of all centers are periodically synchronized by DMA SYNC signal to assure that all NBAs be able to function in synchronism for data transfer from one center to another.

REFERENCES:
patent: 4159532 (1979-06-01), Getson, Jr. et al.
patent: 4181936 (1980-07-01), Kober et al.
patent: 4219873 (1980-08-01), Kober et al.
patent: 4225942 (1980-09-01), Kobs et al.

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