Semiconductor memory device having an error correction circuit a

Details Semiconductor memory device having an error correction circuit a Semiconductor memory device having an error correction circuit a

1992-06-05

1995-01-17

Envall, Jr., Roy N.

Excavating

G06F 1110

Patent

active

053832051

ABSTRACT:
A mask ROM having an ECC for error correction by carrying out operation according to a Hamming matrix in which all but 2 of 6 elements in one column and the other column match each other. The columns correspond to 32 data that will be provided to an external source, and the one column corresponds to the other column by 16 columns. The ECC is implemented so that one half of 32 correction signals with which exclusive ORs are to be taken with 32 data, are generated by a circuit identical to that of a circuit for generating the other half of the 32 correction signals; and the circuit for taking the exclusive ORs from one half of the 32 data and the corresponding correction signals can be used for taking exclusive ORs from the remaining half of the 32 data and the corresponding correction signals. The number of component elements for the correction signal generator and for the data correction circuit, and the number of input signal lines to the data correction circuit are reduced to a half, alleviating the circuit complexity of the entire ECC in comparison with that of a conventional one.

REFERENCES:
patent: 4649540 (1987-03-01), Proebsting
patent: 4780875 (1988-10-01), Sakai
patent: 4958352 (1990-09-01), Noguchi et al.
"Dual ECC Scheme to Reduce Read-Modify-Write Cycles on a 32-bit Data Bus Memory System" IBM Technical Disclosure Bulletin, vol. 28, No. 6, Nov. 1985, p. 2561.

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