Fishing – trapping – and vermin destroying
Patent
1993-11-29
1995-01-17
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437228, 437235, H01L 2144, H01L 2148
Patent
active
053825454
ABSTRACT:
A device and a method of formation on a substrate of a semiconductor interconnection via structure for semiconductor devices is provided. Initially, form a first metal layer on the substrate, a first dielectric layer upon the first metal layer, and a mask upon the dielectric layer with a metal etching pattern therein. Then, etch through the first dielectric layer and the first metal layer to the substrate forming trenches between metal lines formed from the first metal layer covered with the dielectric layer. Next, form a first etch stop layer upon the surface of the first dielectric layer and planarize it, a second dielectric layer above the etch stop layer, and a second etch stop layer on the second dielectric layer. Then, pattern the second dielectric and the second etch stop layer and etch to form a via hole down to a surface of the first metal layer. Then, form a second metal layer and a metal plug in the via hole extending into contact with the first metal layer.
REFERENCES:
patent: 4076860 (1978-02-01), Kuroda
patent: 5187121 (1993-02-01), Cote et al.
K. Ueno et al., "Quarter-Micron Planarized Interconnection Technology with Self-Aligned Plug", IEDM 92-305-307 (1992).
Chaudhuri Olik
Jones II Graham S.
Saile George O.
Tsai H. Jey
United Microelectronics Corporation
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