Process for forming an electrically programmable read-only memor

Details Process for forming an electrically programmable read-only memor Process for forming an electrically programmable read-only memor

1993-09-20

1995-01-17

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 43, 437 48, H01L 2170, H01L 2700, H01L 21265

Patent

active

053825403

ABSTRACT:
An electrically programmable read-only memory cell includes a single crystal silicon pillar having the active region of the memory cell. A memory array of the cells may be configured to act as an EPROM array, an EEPROM array, or a flash EEPROM array. A silicon spacer lies adjacent to each of the silicon pillars and acts as a floating gate for its particular memory cell. A memory cell may have a cell area that is less than one square micron. In an EPROM or a flash EEPROM array, no field isolation is required between the memory cells within the array. Processes for forming the memory cells and the memory array are disclosed.

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Pein, et al.; "A 3-D Sidewall Flash EPROM Cell and Memory Array"; IEEE Electron Device Ltrs.; vol. 14, No. 8, pp. 415-417 (Aug. 1993).

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