Bit error reduction by using checksums in a switching network im

Details Bit error reduction by using checksums in a switching network im Bit error reduction by using checksums in a switching network im

1992-09-30

1995-07-25

Baker, Stephen M.

Excavating

371 82, 371 682, H04Q 124, H04Q 1104

Patent

active

054369150

ABSTRACT:
A method for reducing bit error in a digital communications system including the step of identifying whether a data or information word was correctly switched through a network having at least three switching levels after the data word has been switched by undertaking a parity bit check as well as a bit by bit comparison of the bits in the data word, and an apparatus configured to perform the method. Bit errors are corrected either on the basis of majority decision or by a Statistical evaluation of the bit error rates of the various switching levels of the switching network.

REFERENCES:
patent: 4543651 (1985-09-01), Chang
patent: 4995042 (1991-02-01), Guthaus
patent: 5012465 (1991-04-01), Helou et al.
patent: 5084878 (1992-01-01), Kanekawa et al.
K. Steinbuch, Tashenbuch der Nachrichtenverarbeitung (Springer-Verlag, 1962), pp. 92-93, 154-155.
Patent Abstracts of Japan, vol. 009, No. 123 (E-317), May, 1985, JP-A-60 010 996 (Matsushita), Jan. 21, 1985.

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