Semiconductor memory device comprising a test circuit and a meth

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371 212, 36518901, 365201, G11C 700

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054369118

ABSTRACT:
A semiconductor memory device comprises a memory array. Each bit line pairs connected to a first amplifier. Write buses, read buses and a read/test circuit are provided. A column decoder selects simultaneously every other plurality of bit line pair at the time of testing. The read/test circuit compares the data read out from the selected plurality of bit line pair with the given expected data to provide the comparison result. Then the column decoder selects simultaneously the remaining one other plurality of bit line pairs. The read/test circuit compares data read out from the selected plurality of bit line pair with a given expected data to provide the comparison result.

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