Static information storage and retrieval – Addressing – Sync/clocking
Patent
1982-04-30
1984-03-06
Hecker, Stuart N.
Static information storage and retrieval
Addressing
Sync/clocking
365190, 365210, G11C 700, G11C 800
Patent
active
044357931
ABSTRACT:
A semiconductor memory device is provided, including a plurality of MOS memory cells arranged in a matrix fashion, word lines for selectively transferring an access signal to the MOS memory cells, plural pairs of data lines for effecting data transfer with resepct to the MOS memory cells, sense amplifiers connected to the plural pairs of data lines to amplify data signals on the data lines, and a clock pulse generator connected to produce a clock pulse for activating the sense amplifiers. The memory device further includes a dummy word line arranged in the same manner as the word lines, and a dummy decoder connected to energize the clock pulse generator through the dummy word line so that the clock pulse generator produces a clock pulse to activate the sense amplifiers for preset period of time.
REFERENCES:
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patent: 4094008 (1978-06-01), Lockwood et al.
patent: 4110842 (1978-08-01), Sarkissian et al.
patent: 4162540 (1979-07-01), Ando
patent: 4164791 (1979-08-01), Hamma
patent: 4231110 (1980-10-01), Stinehelfer
patent: 4247791 (1981-01-01), Revell
patent: 4291394 (1981-09-01), Nakane et al.
patent: 4344154 (1982-08-01), Klaas et al.
Hecker Stuart N.
Tokyo Shibaura Denki Kabushiki Kaisha
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