Pillar alignment and formation process

Details Pillar alignment and formation process Pillar alignment and formation process

1993-06-22

1995-07-25

Quach, T. N.

Fishing, trapping, and vermin destroying

437190, 437192, 437228, 437924, H01L 2128

Patent

active

054361990

ABSTRACT:
A process for the formation of pillars (28) in connection with the fabrication of a semiconductor device (10) is disclosed. The process first aligns a lead pattern (30) with an existing structure (24) in the semiconductor device (10). Next, the process aligns a pillar pattern (32) with the lead pattern (30). These two patterns (30, 32) are then transferred downward into respective conductive layers (26, 28) of the semiconductor device (10). An insulating layer (34) is deposted over the conductive layers (26, 28) and etched-back to expose a portion of the pillar (28). A conductive layer (42) is applied over the exposed pillar (28).

REFERENCES:
patent: 4410622 (1983-10-01), Dalal et al.
patent: 4614021 (1986-09-01), Hulseweh
patent: 4674174 (1987-06-01), Kishita et al.
patent: 4954423 (1990-09-01), McMann
patent: 4960489 (1990-10-01), Roeska et al.
Wolf, S., et al., Silicon Processing for the VLSI Era, 1986, Lattice Press, vol I, pp. 473-476.

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